IP Catalog > Foundries > TSMC > Interface IP

Interface IP for TSMC

Welcome to the ultimate Interface IP for TSMC hub! Explore our vast directory of Interface IP for TSMC
All offers in Interface IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (102)
Compare 102 Interface IP for TSMC from 8 vendors (1 - 10)
Filter:
  • 3nm
  • TSMC N3P 1.8V IO Platform supporting cells
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N3P 1.8V IO Platform supporting cells
  • 224G-LR SerDes PHY enables 1.6T and 800G networks
    • Optimized Performance, Power and Area with Design Agility
    • Supports full-duplex 1.25 to 225Gbps data rates
    • Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
    • Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
    • Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects
    Block Diagram -- 224G-LR SerDes PHY enables 1.6T and 800G networks
  • HBM3 PHY V2 (Hard) - TSMC N3P
    • Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
    • 16 independent 64-bit memory channels
    • Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
    • Supports up to 4 trained frequencies with <5us switching time
    Block Diagram -- HBM3 PHY V2 (Hard) - TSMC N3P
  • USB 2.0 femtoPHY - TSMC N3P 1.2V x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC N3P 1.2V x1, North/South (vertical) poly orientation
  • eUSB 2.0 PHY - TSMC N3P x1, North/South (vertical) poly orientation
    • Designed for 7nm processes and below
    • Supports the USB 2.0 protocol and High Speed, Full Speed, and Low Speed data rates
    • eUSB2 PHYs supports USB 2.0, 3.0, 3.1 and 3.2 Device, Host and Dual Role configurations
    Block Diagram -- eUSB 2.0 PHY - TSMC N3P x1, North/South (vertical) poly orientation
  • eUSB 2.0 PHY - TSMC N3E x1, North/South (vertical) poly orientation
    • Designed for 7nm processes and below
    • Supports the USB 2.0 protocol and High Speed, Full Speed, and Low Speed data rates
    • eUSB2 PHYs supports USB 2.0, 3.0, 3.1 and 3.2 Device, Host and Dual Role configurations
    Block Diagram -- eUSB 2.0 PHY - TSMC N3E x1, North/South (vertical) poly orientation
  • USB-C 3.2 DP/TX PHY for TSMC N3P, North/South poly orientation
    • USB-IF certified Synopsys USB 3.2 solution
    • VESA certified Synopsys DisplayPort 1.4 Tx solution
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.2/DisplayPort 1.4 TX PHYs, USB-C 3.2/DisplayPort 1.4 TX controllers with HDCP 2.2 and HDCP 2.2 content protection, verification IP, and IP subsystems
    • Solution supports USB Type-C, SuperSpeed USB 3.2 at 20 Gbps, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.4 TX supporting RBR, HBR1, HBR2 and HBR3 bitrates
    Block Diagram -- USB-C 3.2 DP/TX PHY for TSMC N3P, North/South poly orientation
  • USB-C 3.2 DP/TX PHY, AR - TSMC N3P 1.2V , North/South poly orientation
    • USB-IF certified Synopsys USB 3.2 solution
    • VESA certified Synopsys DisplayPort 1.4 Tx solution
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.2/DisplayPort 1.4 TX PHYs, USB-C 3.2/DisplayPort 1.4 TX controllers with HDCP 2.2 and HDCP 2.2 content protection, verification IP, and IP subsystems
    • Solution supports USB Type-C, SuperSpeed USB 3.2 at 20 Gbps, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.4 TX supporting RBR, HBR1, HBR2 and HBR3 bitrates
    Block Diagram -- USB-C 3.2 DP/TX PHY, AR - TSMC N3P 1.2V , North/South poly orientation
  • USB 3.1 PHY (10G/5G) - TSMC N3P X1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC N3P X1 OTG, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC N3A x1 OTG, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC N3A x1 OTG, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
×
Semiconductor IP