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Interface IP for SMIC

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Compare 221 Interface IP for SMIC from 17 vendors (1 - 10)
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery IP
  • I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus

    • The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-APB is a Master/Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus

    • The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-AHB is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
  • MIPI DPHY-RX

    • Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps

    • Silicon proven in GlobalFoundries 22FDX process

    • Compliant to the MIPI D-PHY spec v1.2

    • Lane type:1 clock + 4 data(D0 is bi-dir)

    • Support for DPHY Ultra Low Power State

    Block Diagram -- MIPI DPHY-RX
  • MIPI DPHY-TX - GlobalFoundries 22FDX process
    • Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
    • Silicon proven in GlobalFoundries 22FDX process
    • Compliant to the MIPI D-PHY spec v1.2
    • Support HiSPi-SLVS TX compatible mode
    Block Diagram -- MIPI DPHY-TX - GlobalFoundries 22FDX process
  • MIPI DPHY
    • Silicon proven in 22, 28, 55, 110nm from Global Foundries, Samsung and SMIC
    • Compliant to the MIPI D-PHY spec v1.1 (SEC28/SMIC55/SMIC110)
    • Lane type:1 clock + 4 data, bi-directional
    • Built-in self test function
    Block Diagram -- MIPI DPHY
  • MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
    • SMIC 130nm
    • Consists of 1 Clock lane and 4 Data lanes
    • Supporting the MIPI Standard 1.1 for D-PHY
    Block Diagram -- MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
    • The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
    • The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-MS-AXI is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
  • USB 2.0 femtoPHY - SMIC 28PS18 x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SMIC 28PS18 x1, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - SMIC 28HKMG18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SMIC 28HKMG18 x1, OTG, North/South (vertical) poly orientation
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