Interface IP for SMIC

Compare 210 Interface IP for SMIC from 19 vendors (1 - 10)

Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB PD 3.1 compliant.
- 8 bit register interface for a low speed processor, or optional I2C interface.
- Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
- SMIC 130nm
- Consists of 1 Clock lane and 4 Data lanes
- Supporting the MIPI Standard 1.1 for D-PHY
10G Combo Serdes for USB/PCIe/Ethernet, SMIC 14FF, N/S orientation
- Supports 1.25G to 10.3125Gbps data rates and compact die area
- Supports up to 25dB channel loss@ 5.15625GHz
- Supports RX loss-of-signal detection
- Supports X1, X2 and X4 lanes
USB1.1 build-in clock PHY, SMIC 55LL
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
USB2.0 build-in clock PHY, SMIC 55LL
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
USB2.0 build-in clock PHY, SMIC 40LL, type-C
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
USB3.0 build-in clock PHY, SMIC 55LL
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
- Compatible with PCIe base Specification
- Full compatible with PIPE4.2 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
V-by-One Rx IP, Silicon Proven in SMIC 40LL
- Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
- Multi-channel shared offset
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in SMIC 65/55SP
- HDMI version 1.4 compliant transmitter
- Supports DTV from 480i to 1080i/p HD resolution
- Supports 24bit, 30bit and 36bit color depth per pixel
- Integrated cable terminator