IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AXI IP > PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface

PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface

Overview

Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is compliant with the PCI Express 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including number, type, and width of AXI interfaces, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. Users may optionally enable the built-in Legacy DMA engine based on the application requirements. Rambus PCIe 3.0 with AXI is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.

Key Features

  • PCIe Interface
    • Complies with the PCI Express Base 3.0 Specification, rev.3.1
    • Supports Endpoint and rootport configuration
    • Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
    • Implements one Virtual Channel
    • Data protection (ECC, ECRC)
    • Maximum payload size of up to 4KB
    • Configurable Receive and Transmit Buffer size
    • Supports SR-IOV, 6 BARs+ EPROM and Open interrupt interface, enabling SATA Express implementation
    • Advanced features include: Advanced Error Reporting (AER), ECRC, MSI, MSI-X, ASPM and legacy power management, Lane Reversal, Hot Plug, peer-to-peer transactions, LTR
    • PIPE 4.0 and PIE-8 compliant PHY interface
      • 32-bit/250MHz in Gen3 mode on x1, x4, x8
      • 16-bit mode supported only on x1, x4, x8 and x16
    • Supported silicon:
      • Process node/foundry agnostic digital controller
      • Interoperable with PIPE 4.0 and PIE-8 compliant analog PHY IP
      • Altera Stratix V, Xilinx Virtex-7
    • AMBA AXI Interface
      • Compliant to the AMBA AXI Specification v1.0 (AXI3) and AMBA AXI Specification v2.0 (AXI4)
      • AXI-Lite Slave interface for IP configuration
      • AXI-Lite Master interface to configure up to 8KB of user defined registers in AXI domain
      • Multiple combination (configurable) of AXI Master, AXI Slave, AXI Stream interfaces
      • Separate clock domains for each AXI interface
      • Configurable data-path (64-bits/128-bits/256-bits)
    • Data Engine and Address translation for PCIe-to-AXI and AXI-to-PCIe transfers
      • Up to 8 DMA Engines for PCIe-to-AXI, AXI-to-PCIe, AXI-to-AXI transfers
        • Up to 4GB (block) or infinite length transfers (packet)
        • Up to 16 outstanding requests
        • Support completion reordering
        • Advanced Scatter-Gather DMA modes
        • Reporting into Scatter Gather Descriptor
        • Caching of descriptors to optimize throughput
      • Up to 16 reconfigurable address translation tables for PCIe interface
      • Up to 8 reconfigurable address translation tables per AXI4 slave interface

    Benefits

    • Engineered for both ASIC/SoC and FPGA implementations. Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL. Fully timing closed on leading edge FPGA from Altera and Xilinx.
    • Advanced AMBA AXI interconnect enables heterogeneous SoC interfacing. Allows AXI3 and AXI4 peripherals to coexist and communicate efficiently through the interconnect interface.
    • Fully configurable communication engine features programmable DMA and Address Translation Windows, allowing flexible and high-performance AXI-to-PCIe, PCIe-to-AXI, and AXI-to-AXI data transfers.
    • Smart ordering rules management enables hazards and deadlocks prevention while ensuring optimized traffic flow.
    • Configurable error detection and reporting enables application specific error management thus simplifying application software.
    • Support for advanced Low Power states enables lower power consumption in energy-conscious applications
    • Flexible PCIe interface configuration in endpoint and root port modes. Includes ECAM support for dynamic configuration of the entire PCIe hierarchy from the AXI domain.
    • Provided with latency optimized Linux x64 PCIe device driver allowing immediate software development. Driver source code available for custom developments

    Block Diagram

    PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface Block Diagram

    Applications

    • HPC,
    • Cloud Computing,
    • AI,
    • Machine Learning,
    • Enterprise,
    • Networking,
    • Automotive,
    • AR/VR,
    • Test and Measurement

    Deliverables

    • Verilog RTL,
    • Supporting Documentation

    Technical Specifications

    Foundry, Node
    Any
    Maturity
    In production
    Availability
    Available
    GLOBALFOUNDRIES
    In Production: 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV
    Pre-Silicon: 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV
    Silicon Proven: 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV
    Renesas
    In Production: 40nm , 55nm , 90nm
    Pre-Silicon: 40nm , 55nm , 90nm
    Silicon Proven: 40nm , 55nm , 90nm
    SMIC
    In Production: 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm G , 130nm LL , 130nm LV
    Pre-Silicon: 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm G , 130nm LL , 130nm LV
    Silicon Proven: 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm G , 130nm LL , 130nm LV
    TSMC
    In Production: 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GOD , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm LVP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
    Pre-Silicon: 28nm HP , 28nm HPL , 28nm HPM , 28nm LP , 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GOD , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm LVP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
    Silicon Proven: 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm LVP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
    UMC
    In Production: 40nm , 40nm LP , 65nm LL , 65nm LP , 65nm SP , 90nm G , 90nm LL , 90nm SP
    Pre-Silicon: 40nm , 40nm LP , 65nm LL , 65nm LP , 65nm SP , 90nm G , 90nm LL , 90nm SP
    Silicon Proven: 40nm , 40nm LP , 65nm LL , 65nm LP , 65nm SP , 90nm G , 90nm LL , 90nm SP
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