MIPI M-PHY IP

Overview

The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).

It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.

Key Features

  • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
  • Dual-simplex point-to-point interface with ultra low voltage differential signaling
  • Slew-rate control for EMI reduction
  • Supports all HS modes (GEAR 1-2)
  • Supports all Type-I LS modes (GEAR 0-7)
  • Supports Type I & II LS mode
  • 1-3Gbps data rate in HS mode
  • 0.01-576Mbps data rate in LS mode
  • Suitable for copper and optical media
  • Modular design to allow for all possible configurations
  • Low power dissipation
  • Uses "Legorithmic" approach to allow for all possible configurations

Block Diagram

MIPI M-PHY  IP Block Diagram

Technical Specifications

SMIC
Silicon Proven: 130nm G
TSMC
Silicon Proven: 28nm HPL , 28nm HPM , 65nm LP
UMC
Silicon Proven: 40nm LP
×
Semiconductor IP