I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus

Overview

Key Features

• Master / Slave I2C Controller Modes:
  • Master – Transmitter
  • Master – Receiver
  • Slave – Transmitter
  • Slave – Receiver
• Supports four I2C bus speeds:
  • Hs-Mode (3.4+ Mb/s)
  • Ultra Fast-Mode (5 mbit/s)
  • Fast Mode Plus (1 Mbit/s)
  • Fast Mode (400 Kb/s)
  • Standard Mode (100 Kb/s)
• I2C compliant features:
  • Multi-Master, Clock Synchronization, Arbitration, SCL held low by Slave, Repeated Start, 7/10-bit addressing, & General Call Addressing
• Parameterized FIFO memory for off-loading the I2C transfers from the processor:
  • Targets embedded processors with higher performance algorithm requirements, by the I2C Controller independently controlling theTransmit or Receive of bytes of information buffered to and from a FIFO.
• System-level features & integration capabilities:
  • CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon SoC Interconnect fabrics
  • Enhanced SCL / SDA spike filtering capabilities
  • Enhanced Repeated Start capabilities
• Optional system-level features & integration capabilities:
  • DMA transfer between the I2C Bus & Memory (SDRAM / SRAM / FLASH)
  • Direct interface to user Registers within ASIC / ASSP / FPGA device, for Master/Slave transfer across the I2C Bus
  • Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
  • SMBus Support:  SMBCLK Clock Low Timeout SMBDAT minimum data hold time
• 13 sources of internal interrupts with masking control
• Compliance with AMBA and I2C specifications:
  • Compliance with AMBA AXI Protocol Specification (V2.0)
  • Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and UM10204 Rev 7 – 1 Oct 2021
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASICdesign flows.

Benefits

• The DB-I2C-MS-AXI Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-MS-AXI contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the I2C transfer to the DB-I2C-MS-AXI Controller. Thus, while the DB-I2C-MS-AXI is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks.

Block Diagram

Deliverables

• Verilog or VHDL RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.

Technical Specifications