Xilinx Buys AutoESL, Securing High-Level Synthesis Capabilities
Xilinx has acquired high-level synthesis start-up AutoESL Design Technologies, bringing the AutoPilot high-level-synthesis tool in-house. AutoPilot accepts a C, C++, or SystemC description of the functionality of an algorithm or task and generates a register-transfer-level (RTL) implementation in Verilog or VHDL. The RTL implementation is then processed through the traditional FPGA RTL logic synthesis, place-and-route, and verification tool flow. Like other high-level synthesis tools, AutoPilot offers time savings in the RTL design and coding process, and speeds the verification process by enabling much of the verification work to be done at the C, C++, or SystemC level, where simulations are dramatically faster than those at the register or gate level.
To read the full article, click here
Related Semiconductor IP
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
Related Blogs
- How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
- A Decade of Building CODECs with High-Level Synthesis
- Building Neural Networks with High-Level Synthesis
- PLD Overview: Xilinx and Altera
Latest Blogs
- Area, Pipelining, Integration: A Comparison of SHA-2 and SHA-3 for embedded Systems.
- Why Your Next Smartphone Needs Micro-Cooling
- Teaching AI Agents to Speak Hardware
- SOCAMM: Modernizing Data Center Memory with LPDDR6/5X
- Bridging the Gap: Why eFPGA Integration is a Managed Reality, Not a Schedule Risk