Building Neural Networks with High-Level Synthesis
Earlier this week, Dave Apte presented a webinar on AI Accelerator Design with Stratus High-Level Synthesis. It was timed for the East Coast and for Europe, so I had to get up at 6:00am to attend, but since I'm still somewhat jet-lagged from getting back from Israel at the weekend, I was awake by 4:30am so I didn't even need my alarm to wake me.
To read the full article, click here
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- A Decade of Building CODECs with High-Level Synthesis
- Take your neural networks to the next level with Arm's Machine Learning Inference Advisor
- Xilinx Buys AutoESL, Securing High-Level Synthesis Capabilities
- How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?