Building Neural Networks with High-Level Synthesis
October 2, 2019
Earlier this week, Dave Apte presented a webinar on AI Accelerator Design with Stratus High-Level Synthesis. It was timed for the East Coast and for Europe, so I had to get up at 6:00am to attend, but since I'm still somewhat jet-lagged from getting back from Israel at the weekend, I was awake by 4:30am so I didn't even need my alarm to wake me.
To read the full article, click here
Related Semiconductor IP
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
Related Blogs
- A Decade of Building CODECs with High-Level Synthesis
- Xilinx Buys AutoESL, Securing High-Level Synthesis Capabilities
- How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
- Embedded Vision: The Road Ahead for Neural Networks and Five Likely Surprises