UVM Sequences Tutorial
May 12, 2015
To verify an RTL design, you must define a stimulus (i.e. what kind of data should be sent to the DUT).
In any test-bench environment, the driver is responsible for signal activities at the bit level. SystemVerilog in functional verification provide this abstraction. It introduces the concept of TRANSACTION, GENERATOR and CHANNEL. Transaction is the actual data item which is generated by the Generator. It is sent to the driver through the Channel to drive it on the DUT interface.
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- Reusable Sequences in UVM
- Virtual Sequences in UVM: Why, How?
- Functional Verification Basics: UVM Tutorial
- Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore Strategy
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing