UVM Sequences Tutorial
May 12, 2015
To verify an RTL design, you must define a stimulus (i.e. what kind of data should be sent to the DUT).
In any test-bench environment, the driver is responsible for signal activities at the bit level. SystemVerilog in functional verification provide this abstraction. It introduces the concept of TRANSACTION, GENERATOR and CHANNEL. Transaction is the actual data item which is generated by the Generator. It is sent to the driver through the Channel to drive it on the DUT interface.
Related Semiconductor IP
- Message filter
- SSL/TLS Offload Engine
- TCP/UDP Offload Engine
- JPEG-LS Encoder IP
- JPEG XS - Low-Latency Video
Related Blogs
- Reusable Sequences in UVM
- Virtual Sequences in UVM: Why? How?
- Reusable Sequences in UVM
- Virtual Sequences in UVM: Why, How?
Latest Blogs
- What’s Your Vector? Synopsys Introduces New ARC VPX6 Digital Signal Processor
- Rambus CXL IP: A Journey from Spec to Compliance
- Alphawave Semi is in Play!
- Vision Transformers Have Already Overtaken CNNs: Here’s Why and What’s Needed for Best Performance
- Tailoring Root Of Trust Security Capabilities To Specific Customer Needs