Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore Strategy
January 6, 2015
In many verification environments, we reuse the same configuration cycles across different testcases. These cycles may involve writing and reading from different configuration and status registers, loading program memories, and other similar tasks to set up a DUT for its targeted stimulus. In many such environments, the time taken during these configuration cycles is very long. Also, there is a lot of redundancy as verification engineers have to run the same set of verified configuration cycles for different testcases leading to a loss in productivity. This is especially true for complex verification environments with multiple interfaces which require different components to be configured.
To read the full article, click here
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related Blogs
- Running X-Propagation with Low-Power Simulation
- Interactive Debugging: Reduce Your Simulation Debug Turn-Around-Time
- Unlock early software development for custom RISC-V designs with faster simulation
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
Latest Blogs
- MIPI: Powering the Future of Connected Devices
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development