The Increasing Role of SystemC in System Design
Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on.
As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers with many different backgrounds. Every so often one of them asks, "Why SystemC?" Some software engineers look at SystemC and decide that it looks like a real mess. They mention things like:
- SystemC has complex classes built with C++
- It uses strange macros like SC_MODULE, SC_METHOD, and SC_HAS_PROCESS
- Sometimes it can be difficult to find the cause of compilation errors
- SystemC takes a long time to compile
- Generally it doesn't provide much benefit for all this complexity
They ask, "what is wrong with plain C++ or even plain old C?" Most of the time they ask these questions because they don't understand how everything fits together.
To read the full article, click here
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related Blogs
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
- Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
- What Does the Future Hold for AI in Chip Design?
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet