Synopsys Enhances ARC Processor Core With Superscalar, DSP Capabilities
November 16, 2017
By adding a second front-end instruction decoder to the ARC HS3x high-end 32-bit RISC architecture, along with doubling the number of ALUs, Synopsys has created its latest ARC HS4x processor IP core family (Figure 1). The estimated performance increase over an ARC HS3x predecessor at the same clock speed can be as high as 40%, according to the company, with only modest die size and power consumption impacts. And via the inclusion of DSP enhancements akin to those initially launched with the mid-range ARC EMxD family, the HS3x-to-HS4xD (D=DSP) performance boost on code leveraging the associated expanded instruction set can be as much as 2x.
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Related Semiconductor IP
- Memory management unit (MMU) option for ARC HS5x and HS6x processors
- L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
- DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications
- Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
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- Adapteva's Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- Can we really find a way to speed-up Processor & DSP core designs?
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