Synopsys Enhances ARC Processor Core With Superscalar, DSP Capabilities
November 16, 2017
By adding a second front-end instruction decoder to the ARC HS3x high-end 32-bit RISC architecture, along with doubling the number of ALUs, Synopsys has created its latest ARC HS4x processor IP core family (Figure 1). The estimated performance increase over an ARC HS3x predecessor at the same clock speed can be as high as 40%, according to the company, with only modest die size and power consumption impacts. And via the inclusion of DSP enhancements akin to those initially launched with the mid-range ARC EMxD family, the HS3x-to-HS4xD (D=DSP) performance boost on code leveraging the associated expanded instruction set can be as much as 2x.
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