Synopsys Enhances ARC Processor Core With Superscalar, DSP Capabilities
November 16, 2017
By adding a second front-end instruction decoder to the ARC HS3x high-end 32-bit RISC architecture, along with doubling the number of ALUs, Synopsys has created its latest ARC HS4x processor IP core family (Figure 1). The estimated performance increase over an ARC HS3x predecessor at the same clock speed can be as high as 40%, according to the company, with only modest die size and power consumption impacts. And via the inclusion of DSP enhancements akin to those initially launched with the mid-range ARC EMxD family, the HS3x-to-HS4xD (D=DSP) performance boost on code leveraging the associated expanded instruction set can be as much as 2x.
To read the full article, click here
Related Semiconductor IP
- ARC HS48 32-bit, dual-issue processor with MMU, ARCv2 ISA, for embedded Linux applications
- ARC HS46 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
- ARC HS44 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
- ARC HS48x2 dual-core version of dual-issue HS48 processor with MMU, ARCv2 ISA, for embedded Linux applications
- ARC HS48x4 is quad-core version of dual-issue HS48 processor with MMU, ARCv2 ISA, for embedded Linux applications
Related Blogs
- Synopsys' EM5D and EM7D Processor Cores: The ARC Architecture Gains DSP Capabilities
- What’s Your Vector? Synopsys Introduces New ARC VPX6 Digital Signal Processor
- Adapteva's Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- Can we really find a way to speed-up Processor & DSP core designs?
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design