Can we really find a way to speed-up Processor & DSP core designs?
Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When you discover the “Set-up” and “Hold” time in a DFF feature list, at first you don’t realize that these very specific DFF features will ultimately dictate the Supercomputer minimum cycle time, so the machine most important performance (modest at that time, as the maximum frequency was 20… MHz!).
Thanks to this first experience, I was not so surprised when ACRI Engineering management had announced in 1994 to TI sales guys (including myself) that they will preferably use custom Flip Flops, designed on request by Phoenix VLSI, a very talented design team located in the UK. In fact, if you can reduce by design techniques the Set-up and Hold time to zero, or even to a negative number, you probably increase the basic cycle time by 20% or so. The only problem was that “somebody” had to run characterization on these custom cells, automatically generates the models you need to simply pass through the ASIC design flow… Somebody was again me, and I enjoyed spending 3 months in TI Bedford, in the north of the UK (during winter) that I certainly recommend to whoever thinks his life is boring: after Bedford, any location is like Disneyland.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
Related Blogs
- Adapteva's Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- Synopsys Fields Processor Core for Neural Network Computer Vision Applications
- Next-Gen Cadence Tensilica Vision Processor Core Claims Big Performance, Energy Consumption Gains
- Tensilica Vision P6 Processor Core Adopts Deep Learning-Focused Enhancements
Latest Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
