Can we really find a way to speed-up Processor & DSP core designs?

By SemiWiki

June 24, 2013

Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When you discover the “Set-up” and “Hold” time in a DFF feature list, at first you don’t realize that these very specific DFF features will ultimately dictate the Supercomputer minimum cycle time, so the machine most important performance (modest at that time, as the maximum frequency was 20… MHz!).

Thanks to this first experience, I was not so surprised when ACRI Engineering management had announced in 1994 to TI sales guys (including myself) that they will preferably use custom Flip Flops, designed on request by Phoenix VLSI, a very talented design team located in the UK. In fact, if you can reduce by design techniques the Set-up and Hold time to zero, or even to a negative number, you probably increase the basic cycle time by 20% or so. The only problem was that “somebody” had to run characterization on these custom cells, automatically generates the models you need to simply pass through the ASIC design flow… Somebody was again me, and I enjoyed spending 3 months in TI Bedford, in the north of the UK (during winter) that I certainly recommend to whoever thinks his life is boring: after Bedford, any location is like Disneyland.

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