Programming AXI-ACE VIP to Generate Error Scenarios
March 19, 2015
VIP manager Tushar Mattu of Synopsys describes how to program AXI-ACE VIP to generate error scenarios
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
Related Blogs
- Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
- Oxford Digital Offers Small Audio DSP Core With Graphical Programming
- Media Tablet & Smartphones to generate $6 Billion market in... power management IC segment by 2012, says IPnest
- A Strategy to Verify an AXI/ACE Compliant Interconnect (2 of 4)
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained