Physical AI at the Edge: A New Chapter in Device Intelligence

By Iri Trashanski

December 15, 2025

Ceva’s 2025 Technology Symposium series, held in Shanghai, Hsinchu and Herzliya , brought together a global community of engineers, product leaders, and ecosystem partners. Each location had its own flavor, but a single theme ran through every discussion: how to bring meaningful intelligence to the edge of every device.

This year, that shift was most visible in the way physical AI has matured. No longer simply “AI on the device,” Physical AI now describes architectures that sense, process, and act locally, under tight power, cost, and latency constraints. And demand is rising across markets, from wearables and consumer devices to automotive, industrial systems, and beyond.

Three Regions, One Direction

Shanghai conversations highlighted commercialization at scale, where vendors are bringing edge AI into high-volume products faster than ever. Hsinchu showcased scalability, especially how wireless connectivity and AI co-processing are converging in highly constrained SoCs. And in Herzliya  engineering realities took center state: advances in signal processing advances, energy-efficient AI, and low-power cellular IoT.  Together, these perspectives pointed to a consistent architectural model built on three layers:

• Connectivity as the transport layer, where AI runs in multiple locations and is enabled by power-efficient wireless across Wi-Fi 7, Bluetooth, UWB and 5G.
• Sensing as the perception and experience layer, using radar, vision, inertial, and multimodal inputs for contextual awareness
• Inference as the decision layer, where the right AI engine in the right place makes split-second choices at the edge.

Individually, each is important. Together, they define how physical AI comes to life in real products.

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Designing for Constraint, Not Abundance

A clear takeaway across the symposium series was how sharply engineering priorities have shifted. Edge design is now defined by constraints: power budgets, memory footprint, thermal envelope, integrated solutions and system cost. These are not afterthoughts, they are the primary design drivers that determine whether a product is viable.

Speakers shared how they are tuning architectures to specific use cases: reducing inference latency, trimming model size, and keeping memory utilization in check. Others focused on maintaining SKU flexibility across regions while regulatory and feature requirements.

In this context, physical AI, is not about peak compute.  Its value lies in efficiency, predictability, and adaptability.

From IP to Execution

Another strong theme was that IP blocks alone are no longer enough. Design teams want integration support, unified toolchains, and partners who help them move faster at the system level.

Ceva’s sessions on multi-protocol connectivity, AI co-processing, and unified development tools resonated strongly, reinforced by partner presentations showing these capabilities in real products or close to launch. Across all three events, the appetite for joint enablement and co-design was unmistakable. The mindset is shifting from selecting blocks to selecting a partner who helps deliver a complete system.

Closing Thought

What stood out most this year was the industry’s readiness. Physical AI is no longer experimental or optional; it is being designed into high-volume devices now and reshaping how teams think about silicon, software, and systems.

Thank you to our customers, partners, and speakers for making the 2025 Ceva Technology Symposium series so energizing. Your insights are helping define how we deliver the next generation of edge intelligence.