Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
In 2021, PCI-SIG® released the latest version of the PCI Express® specification PCIe® 6.0. PCIe 6.0 has a raw data rate of 64 GT/s and double the bandwidth of PCIe 5.0 (32GT/s) to meet industry demand for a high-speed, low latency interconnect. It is a scalable interconnect solution for data-intensive markets like data centers, AI/ML, high-performance computing (HPC), and automotive.
In our recent blog, PCI Express Surges Forward: High Bandwidth Interconnect with PCIe 6.0 we talked about the changes that are introduced in PCIe 6.0. In this blog we will discuss the Forward Error Correction (FEC) mechanism in PCIe 6.0, why it is required, and what verification solution Synopsys offers to cover this feature.
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Related Semiconductor IP
- PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
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- PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 6.0 / CXL 3.0 PHY & Controller
Related Blogs
- Demystifying Forward Error Correction (FEC) in PCIe 6.0
- Navigating the Complexity of Address Translation Verification in PCI Express 6.0
- Streamline PCIe 6.0 Switch Design with Effective Verification Strategies
- Unraveling the Newly Introduced Segmentation in PCIe 6.0
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