Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
August 24, 2022
In 2021, PCI-SIG® released the latest version of the PCI Express® specification PCIe® 6.0. PCIe 6.0 has a raw data rate of 64 GT/s and double the bandwidth of PCIe 5.0 (32GT/s) to meet industry demand for a high-speed, low latency interconnect. It is a scalable interconnect solution for data-intensive markets like data centers, AI/ML, high-performance computing (HPC), and automotive.
In our recent blog, PCI Express Surges Forward: High Bandwidth Interconnect with PCIe 6.0 we talked about the changes that are introduced in PCIe 6.0. In this blog we will discuss the Forward Error Correction (FEC) mechanism in PCIe 6.0, why it is required, and what verification solution Synopsys offers to cover this feature.
To read the full article, click here
Related Semiconductor IP
- PCIe 6.0 Retimer Controller with CXL Support
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
- PCIe 6.0 (Gen6) Premium Controller
- Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
Related Blogs
- Introduction of Precoding in PCIe 6.0
- Insights Into the Evolutions and Optimizations of PCIe 6.0
- Navigating the Complexity of Address Translation Verification in PCI Express 6.0
- PCIe 6.0 Address Translation Services: Verification Challenges and Strategies
Latest Blogs
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security