Tensilica Vision P6 Processor Core Adopts Deep Learning-Focused Enhancements
May 26, 2016
Just last October, Cadence announced the then-latest generation in its computer vision processor core roadmap, the Tensilica Vision P5. Only seven months later, the Vision P5 has been superseded by the Vision P6 (Figure 1). This rapid product development pace reflects the equally rapid expansion and evolution of embedded computer vision applications. According to Cadence’s Chief Technology Officer Chris Rowen and Director of Product Marketing Pulin Desai, the company's new vision core is the beneficiary of significant experience amassed from an abundance of customers and applications. It's especially optimized for convolutional neural networks (CNNs) and other deep learning techniques.
Related Semiconductor IP
- Imaging and Computer Vision Processor
- Intelligent Vision Processor
- Image signal processor to advance vision systems for IoT and embedded markets
- ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
Related Blogs
- Next-Gen Cadence Tensilica Vision Processor Core Claims Big Performance, Energy Consumption Gains
- The CEVA-XM6 Vision Processor Core Boosts Performance for Embedded Deep Learning Applications
- 6 reasons deep learning accelerators need vision processors
- GPP, GPU or Embedded Vision Dedicated Processor?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?