PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking
This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos.
The Verification demo was centered around the PCIe 5.0 VIP acting as a Root Complex talking to our Integrated IP for PCIe 5.0 Endpoint. We specifically highlighted one of our PCIe 5.0 tests from the UVM source code test suites. The demo walked users through linkup and training including equalization. The test executed configuration of the BAR and then a series of DMA transfers. The demo also showcased natively integrated Verdi Protocol Analyzer for easy and fast transaction level debug.
To read the full article, click here
Related Semiconductor IP
- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits
- PCIe 5.0 (Gen5) Premium Controller with AMBA bridge II
Related Blogs
- Ultra Ethernet Consortium Set to Enable Scaling of Networking Interconnects for AI and HPC
- CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs
- AI-Based Sequence Detection for IP and SoC Verification & Validation
- Empowering AI-Enabled Systems with MIPI C/D-PHY Combo IP: The Complete Audio-Visual Subsystem and AI