PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking
This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos.
The Verification demo was centered around the PCIe 5.0 VIP acting as a Root Complex talking to our Integrated IP for PCIe 5.0 Endpoint. We specifically highlighted one of our PCIe 5.0 tests from the UVM source code test suites. The demo walked users through linkup and training including equalization. The test executed configuration of the BAR and then a series of DMA transfers. The demo also showcased natively integrated Verdi Protocol Analyzer for easy and fast transaction level debug.
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Multi-port Switch
- PCIe 5.0 Controller with AXI
- PCIe 5.0 Controller
- PHY for PCIe 5.0 and CXL
- PCIe 5.0 Integrity and Data Encryption Security Module
Related Blogs
- Ultra Ethernet Consortium Set to Enable Scaling of Networking Interconnects for AI and HPC
- CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs
- Unveiling Ultra-Compact MACsec IP Core with optimized Flexible Crypto Block for 5X Size Reduction and Unmatched Efficiency from Comcores
- Faster, Higher Capacity Emulation and Prototyping for AI Workloads
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility