PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
Rambus announced this week that it demonstrated for the first time a PCI Express 5.0 Controller IP (PCIe 5 Controller) operating at 32 GT/s on a leading FPGA platform.
“We’ve achieved a new industry benchmark with the demonstration of our PCIe 5.0 Controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general manager of Interface IP at Rambus. “With the importance of FPGAs in markets from defense to the data center, this solution developed by the newly-acquired PLDA team expands the Rambus portfolio and offers the next level of performance for mission-critical applications.”
Beyond the technical feat, you might wonder: what are the benefits for Rambus customers?
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Controller
- PCIe 5.0 Controller with AXI
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits
Related Blogs
- Rambus Achieves PCI Express® (PCIe®) 5.0 Compliance for PCIe 5.0 Controller IP and Inspector PCIe 5.0 Interposer with Diagnostic IP
- Integrated MIPI Display IP Solution Delivers Performance for New Use Cases
- Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
- Synopsys IP Passes PCIe 5.0 Compliance and Makes Integrators List