Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
December 1, 2017
On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional verification runs for server and SoC designs using the PCIe 5.0 specification. It also gives designers access to the Indago Protocol Debug App.
To read the full article, click here
Related Semiconductor IP
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
Related Blogs
- PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking
- Industry's First Adopted VIP for PCIe 7.0
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
- PCIe PIPE 4.4.1: Enabler for PCIe Gen4
Latest Blogs
- Silicon Insurance: Why eFPGA is Cheaper Than a Respin
- One Bit Error is Not Like Another: Understanding Failure Mechanisms in NVM
- Introducing CoreCollective for the next era of open collaboration for the Arm software ecosystem
- Integrating eFPGA for Hybrid Signal Processing Architectures
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity