Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
December 1, 2017
On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional verification runs for server and SoC designs using the PCIe 5.0 specification. It also gives designers access to the Indago Protocol Debug App.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking
- Industry's First Adopted VIP for PCIe 7.0
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
- PCIe 4.0: A Quick Primer on New Features
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power