Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for PCIe 5.0 that continues to blaze the trail with new benchmarks for power, performance, and area.
The PCIe standard has been around for nearly 20 years. A diverse range of applications, bandwidth needs, and form factors drive the need for rate scaling of the protocol.
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Related Semiconductor IP
- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits
- PCIe 5.0 (Gen5) Premium Controller with AMBA bridge II
Related Blogs
- Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
- Signing off PCIe 5.0 Verification with Synopsys VIP
- PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
- Synopsys IP Passes PCIe 5.0 Compliance and Makes Integrators List