Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
April 14, 2021
Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for PCIe 5.0 that continues to blaze the trail with new benchmarks for power, performance, and area.
The PCIe standard has been around for nearly 20 years. A diverse range of applications, bandwidth needs, and form factors drive the need for rate scaling of the protocol.
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Multi-port Switch
- PCIe 5.0 Controller with AXI
- PCIe 5.0 Controller
- PHY for PCIe 5.0 and CXL
- PCIe 5.0 Integrity and Data Encryption Security Module
Related Blogs
- Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
- Rambus Achieves PCI Express® (PCIe®) 5.0 Compliance for PCIe 5.0 Controller IP and Inspector PCIe 5.0 Interposer with Diagnostic IP
- Understanding PCIe 6.0 Shared Flow Control
- Building Verification Infrastructure for Complex PCIe Verification
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility