Moore's Law and 28nm Yield
January 25, 2010
This blog is a follow-up to my second most viewed page Moore’s Law and 40nm Yield, with a strong recommendation of how to design for yield at the advanced nodes (32/28/22nm) with Verify High-Sigma design technology.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- Moore’s Law and 40nm Yield
- Moore's Law Has Stopped at 28nm!
- Four questions about Moore's Law, 28nm and the future of IP design
- 28nm Was Last Node of Moore's Law
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