Moore’s Law and 40nm Yield
November 29, 2009
To follow up one of my most popular blogs TSMC 40nm Yield Explained!, here is a closer look at the 40nm yield issues that currently plague the semiconductor industry. It’s a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level.
Related Semiconductor IP
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
- Verification IP for DisplayPort/eDP
- Wirebond Digital and Analog Library in TSMC 65nm
Related Blogs
- Moore's Law and 28nm Yield
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC explains 40nm yield problems, metal-gate stacks and why 100 per cent utilisation is bad
- TSMC 40nm Yield Explained!
Latest Blogs
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security