Moore’s Law and 40nm Yield
November 29, 2009
To follow up one of my most popular blogs TSMC 40nm Yield Explained!, here is a closer look at the 40nm yield issues that currently plague the semiconductor industry. It’s a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level.
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related Blogs
- Moore's Law and 28nm Yield
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC explains 40nm yield problems, metal-gate stacks and why 100 per cent utilisation is bad
- TSMC 40nm Yield Explained!