Moore’s Law and 40nm Yield
November 29, 2009
To follow up one of my most popular blogs TSMC 40nm Yield Explained!, here is a closer look at the 40nm yield issues that currently plague the semiconductor industry. It’s a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level.
Related Semiconductor IP
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
Related Blogs
- Moore's Law and 28nm Yield
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC 40nm Yield Explained!
- Moore's (Empirical Observation) Law!