LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

By Shyam Sharma

July 31, 2025

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market today where it’s used in a diverse set of applications that spans mobile/handheld devices, IoT, client and server, automotive, virtual reality/gaming consoles, robotics, data centers, and AI applications, just to name a few.

JEDEC has just released the LPDDR6 specification that is expected to take the LPDDR DRAM market to new heights with data transfer speeds that can reach up to 14.4Gbps, which is a 50% improvement over LPDDR5X speeds. LPDDR6 device density can range from 4 GB to 64 GB.

Other important features of LPDDR6 devices include:

• Two sub-channels per device: LPDDR6 has x12 data bus per sub-channel, making the total device data width x24. This means that LPDDR6 is the first DRAM to have a non-power-of-2 data width. However, the actual data transfer is still 32 bytes, with other data bits designed to carry metadata.
• Metadata built into the data packets: This is the first time LPDDR DRAMs have moved away from dedicated pins to carry metadata information like data mask, data bus inversion, Link Error Correction Code (ECC), just to name a few. This allows for enhanced RAS coverage, which has been an important feature asked for by system designers for a long time.
• Pow row activation count: Row hammer-related issues have been a significant data integrity challenge for DRAMs for a long time. In the past, other DRAM devices like LPDDR5, DDR5, HBM4, etc., have relied upon refresh management to mitigate the risk to some extent. LPDDR6 is the first DRAM standard to address this, where both the host and the DRAM need to keep track of the activation counts. If activation counts are tracked as intended, it can effectively mitigate the possibility of data corruption caused by row hammering.
• Low-power optimizations:
  • Every other command inputs: LPDDR6 commands can only be started on even cycles and require clock synchronization to determine even/odd cycles, reducing the command I/O power significantly. 
  • Dynamic Voltage Frequency Scaling (DVFS) options: DVFSH (High), DVFSL (Low), DVFSB (VDD2D): LPDDR6 supports multiple voltage rails. The host can use the Dynamic Voltage Frequency Scaling transitions to switch between high, low, and VDD2D voltage rails. This is an improvement from the high and low rail selection that was offered by LPDDR5/5X devices.
• Command bus parity: LPDDR6 devices optionally support CA parity. When enabled, DRAM requires the host to calculate even bit parity , which is then checked by the DRAM to protect commands against possible link errors.
• Refresh optimization: LPDDR6 supports dual bank refresh operation where the host can control which two banks are going to be refreshed, instead of the round-robin fashion all previous DRAM generations have supported. This allows significant scheduling optimizations that the host can utilize while scheduling per-bank refreshes, which are important to keep the integrity of stored data.
• System meta mode: LPDDR6 devices can optionally support carving out a part of the memory array to assign to metadata, which can be used by the host to implement any meta mode functions. Data can be transferred between the main memory array and the carved out metadata memory array using metadata registers, which are available per bank.
• Efficiency Mode: LPDDR6 devices can use the dynamic or static efficiency mode to save on the I/O Power and double the device density. Static Efficiency mode allows combining 2 LPDDR6 devices while keeping the same number of pins at the package level.
• Enhanced RAS (Reliability, Availability, and Serviceability: LPDDR6 device supports several RAS features. Some of the important features include:
  • Error detection, correction, and scrub: LPDDR6 device supports link and on-die ECC, which allows for single-bit error (SBE) corrections/multi-bit error (MBE) detection. The host can also choose to use Error Diagnostic Coverage (EDC) Detection mode for link error, which allows for 100% detection coverage of SBE/MBE errors. Additionally, LPDDR6 devices can support DDR5-style auto and manual error scrub operation, allowing DRAM to internally read, detect/correct errors, and write back corrected data bits to the memory array.
  • Fault diagnostics and notification: LPDDR6 supports a set of four fault registers that can inform the host about critical errors like ECC, parity, or PRAC-related errors. It also supports a dedicated alert signal to notify the host. This is a first for any LPDDR devices so far.

LPDDR6 Vs LPDDR5/LPDDR5X

While LPDDR6 standard has many new features described above, there are some features that LPDDR5/5X devices supports but are no longer available in LPDDR6. The table below lists a summary of LPDDR5/5X Vs LPDDR6 features (including optional features):

Cadence Verification IPs offers a comprehensive memory subsystem solution that includes LPDDR6 memory model, DFI VIPs, and a system performance analyzer tool for the recently released LPDDR6 standard. Cadence also supports Verification IPs for all previous generation LPDDR devices like LPDDR5/5x, LPDDR4, LPDDR3, LPDDR2, etc.

The LPDDR6 memory model comes with comprehensive functional coverage, assertion coverage, and a verification plan. 

Learn more about Cadence LPDDR6 VIP at Cadence VIP Memory Models Website, and stay tuned for my next blog about the LPDDR6 verification challenges and solutions offered by Cadence.

If you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com.