The LPDDR6 Verification IP provides an effective & efficient way to verify the LPDDR6 components of an IP or SoC. The VIP is lightweight, featuring easy-to-use plug-and-play components, so there is no impact on the design cycle time.
LPDDR6 Verification IP
Overview
Key Features
- Supports LPDDR6 memory with all compliant vendors.
- Supports all LPDDR6 densities up to 48 Gb.
- Supports x12 DQ and 24 burst length (256 bits of data 32 bits of – not data)
- LPDDR6 Introductory data rate – 10.667 Gbps
- LPDDR6 Highest defined data rate – 14.4 Gbps (double LPDDR5)
- LPDDR6 introductory bandwidth – 32 Gbps
- Support per-row activation counting PRAC
- Four bank groups per sub-channel, four banks per bank group
- Support ALERT (new) signals per channel
- Support metadata 16 bit (Host ECC, EDC, and Memory tagging) (LP6 co DMI)
- Support RAS Focused (16 bits) – Link Protection
- Supports all LPDDR6 mode registers
- Supports Direct refresh management
- Supports capturing of all the valid LPDDR6 commands as per the specs
- Constantly monitors LPDDR6 flow during simulation
- Supports Programmable READ/WRITE Latency timings
- Support all LPDDR6 trainings
- Support for Power Down features
- Error injection is available for extensive failure testing
- Extensively detailed simulation & debug logs
- Error ID mechanism to show the spec section in the description of the obtained error
- Supports Constraint Randomization
- Callbacks in the host device for user processing of data
- Complete test suite to verify each feature of the LPDDR6 standard
- Built-in Coverage Analysis
- Graphical analyzer for easy debugging
- Transactions logger that prints all the logging information.
- Functional coverage for complete LPDDR6 features
- Monitors, detects, and notifies the testbench of significant events such as transactions, warnings, timing, and protocol violations
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide complete solution and easy integration in IP and SoC environment
Block Diagram
Deliverables
- LPDDR6 Functional memory controller BFM/Agent
- LPDDR6 SDRAM Model
- LPDDR6 Monitor and Scoreboard
- LPDDR6 PHY BFM Model
- LPDDR6 PHY Monitor and Scoreboard
- Test Environment & Test Suite:
- Basic Directed Tests
- Random Tests
- Error Injection Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Technical Specifications
Short description
LPDDR6 Verification IP
Vendor
Vendor Name