Intel -- The Litmus Test
June 24, 2015
How will we bridge the gap between widely different estimates for transistor cost to scale to upcoming nodes? Whom are we to believe?
Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore's Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip
- UALink: Powering the Future of AI Compute
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- How the SiFive HiFive Premier P550 is Accelerating Linux Ecosystem Adoption
Latest Blogs
- Evolution of CXL PBR Switch in the CXL Fabric
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success