Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip
Late this summer, Synopsys and Intel marked a milestone achievement at the Intel Innovation 2023 conference, with the world’s first Universal Chiplet Interconnect Express (UCIe) interoperability test chip demonstration showing robust UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP.
The successful UCIe test chip demonstration is the latest achievement over the course of a long-standing collaboration between Synopsys and Intel. Seeking to demonstrate working interoperability, Intel got the process started by reaching out to Synopsys, one of the first in the industry with available UCIe IP. The effort involved multiple teams spread across the world. In addition to package design, the teams engaged in a substantial amount of work pre-silicon to uncover issues by simulating each test chip using Synopsys VCS® functional verification solution.
Intel’s test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology. It was paired with a Synopsys UCIe IP test chip, fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- The UCIe CONTROLLER IP
- UCIe D2D Adapter
- Simulation VIP for UCIE
- UCIe Verification IP
Related Blogs
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- ARM and Mentor Team Up on Test
- Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design