IEDM: Novel Interconnect Techniques Beyond 3nm

By Cadence

January 30, 2020

During the short course on the Sunday before IEDM, Chris Wilson of imec presented Novel Interconnect Techniques for Advanced Devices Beyond 3nm. In some ways, this is a complementary presentation to the one given by TSMC that I covered last week in IEDM: TSMC on 3nm Device Options.

Going forward requires DTCO and scaling boosters, such as self-aligned block, fully self-aligned via, supervia (going up more than one level), and buried power rail (BPR). Chris went over the process implications of many of these, but I won't repeat everything here, not least because I'm not a process expert.

But here is one example, the fully self-aligned via. Fully self-aligned means that the via is confined by both the interconnect layer underneath and the one on top, as in the diagram on the right below, so that the via metal is precisely where it is required to join the two layers.

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