Xilinx announces first stacked silicon interconnect technology
Xilinx Inc. announced the industry’s first stacked silicon interconnect technology. It proposes to deliver breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.
3D packaging approach
L-R: Xilinx's Dave Myron, Suresh Ramalingam and Neeraj Varma discuss the first stacked silicon interconnect technology.
Xilinx has taken a 3D packaging approach that makes use of passive silicon-based interposers, microbumps and through-silicon vias (TSV) to deliver multi-die programmable platforms. As the interposer is passive, it does not dissipate any heat beyond what’s consumed by an FPGA die.
To read the full article, click here
Related Semiconductor IP
- MIPI SoundWire I3S Peripheral IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
Related Blogs
- The silicon behind Android
- Fab allocation back on the agenda
- Open-Silicon adds Silicon Logic Engineering - for a good reason
- What's happening on the 450mm wafer front?
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained