Introducing FPGA-Based Acceleration for High-Frequency Trading

By EETimes

July 30, 2014

Before we start, I would like to note that this column came out of a detailed case study that was conducted while I worked at SilMinds on the productization of a set of patented, high-performance, decimal floating-point arithmetic IP cores as a potential real-time FPGA solution for accelerating accuracy-demanding, computationally intensive high-frequency trading (HFT) platforms.

Emerging capital market HFT is bringing strong FPGA use cases in networking, messaging, and financial computing acceleration. Stake holders include institutional and proprietary investors, exchanges, and electronic communication networks (ECNs) offering 24x7 exchange-like services, brokerages, and third-party market data providers. In both the US and UK markets, HFT has averaged approximately 60% of equity trading volume throughout the past five years.

Stimulated by sub-millisecond buy and sell trade orders, the aforementioned entities are engaging in a speed race to cut down market data round-trip latency. The trader demands fresher market data to enable better qualified order executions that would reach the exchange's order matching engine faster than those of competitors. Various latencies, within and across platforms, are being pressed into the (sub)-microsecond order.

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