Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters

By Andy Jaros

October 23, 2025

Data converters are the gateways that connect the real (analog) world to the digital world. They are available as discrete devices, integrated into microcontrollers and FPGAs as well as licensable intellectual property (IP) in nearly all popular foundry process nodes.   

With the explosion of AI processing at the edge and the rising cost of developing ASICs at advanced process nodes, the need has never been greater for ASICs and SoCs to connect to a wide variety of sensors available today and into the future. 

Data converters come in a wide range of performance levels (speed, resolution, power, linearity) depending on the application requirements.  Applications such as 5G/6G, radar, optical communications, electronic warfare, and test and measurement collect vast amounts of data. To make mass data movement more manageable, high-speed data converters serialize data movement which is invaluable to reduce pin count and packaging costs compared to parallel data paths. 

Historically, these data converters typically followed the JEDEC JESD204 standard, which was first published in 2006 and subsequently updated to JESD204A, JESD204B, JESD204C, and, most recently, JESD204D.  Table 1 highlights the main differences between the different versions, with the last two releases, spaced six years apart, supporting higher transfer rates and other options.  

Many, if not the majority, of wireless communications, radar, and test and measurement systems rely on JESD-compliant data converters integrated in FPGAs from Xilinx and Altera, who have successfully serviced the market for small to medium-sized production volumes. When system volumes increased to the point where annual FPGA purchases exceeded the cost of developing an ASIC, many programs converted their designs to ASICs, integrating the data converters but losing the flexibility that FPGAs provide. 

Today, the leading driver to move from FPGA to ASIC has shifted reduce SWaP-C (size, weight, power, and cost). Additionally, there is a growing movement for companies wanting to establish a secure supply chain through their own chip development to avoid reliance on potential FPGA chip obsolescence. This is especially true when the product is expected to have a 10-year, 20-year, or longer lifespan.  

We are now at an inflection point where combining eFPGA with data converters enables ASICs and SoCs to address the performance, power, and supply chain worries while still retaining the re-programmability users have long been accustomed to. However, eFPGA is expensive in terms of silicon area from an ASIC designer’s perspective, so judicious use and appropriate sizing of the amount of eFPGA integrated is critical to maximize SWaP-C benefits. 

Some Examples of Judicious Use of eFPGA with Data Converters are: 

• Dynamic Data Filtering: The amount of reconfigurability depends on the filter and the availability of DSP MACs in the eFPGA fabric.  Small, single-rate FIR filters need ~500 LUTs, moderate multi-rate polyphase FIR for decimation/interpolation can take up to 10,000 LUTs, while large multi-channel/high parallelism filters require up to 50,000 LUTs. Moreover, filtering algorithms improve over the lifetime of a deployed product; eFPGA enables the flexibility to update the filtering algorithms as they evolve. 
• Link Layer Encoding and Decoding:  Supports converting packet header formats:  up to 1,000 LUTs for a single high-speed lane, implementing basic line encoding/decoding (8b/10b or 64b/66b + scrambler/descrambler + sync-word detection + simple PCS logic). 
• Lane De-Skew: Requires up to 200 LUTs per lane for control/stat/counter and comparison logic plus block RAM (BRAM) for elastic buffers/FIFOs. For 8 lanes, this adds up to around 1600 LUTs or well under a third of a square millimeter in 18A.  
• Forward Error Correction:  The amount of LUTs required varies from <1K LUTs (Convolutional code + Viterbi), 10K LUTs (Reed-Solomon) or >10Ks LUTs (Turbo code, LDPC) depending on the type of FEC algorithm. 

While any one of the above use cases would absolutely be smaller and lower power as hard ASIC gates, the key takeaway for the ASIC designer is that these circuits can be changed post-manufacturing. This enables malleable data and control paths to support data from legacy, current, and future sensors, expanding target markets and extending system lifespans. 

In addition to the specific use cases above, FPGA functionality in an ASIC is better than embedded processors for: 

• Deterministic latency requirements across multiple lanes and devices, where instruction and data reads/writes to memory cannot guarantee an on-time result 
• Custom alignment of FIFOs, timing calibration logic, or new synchronization methods in phased-array radar or massive MIMO antennae. 
• Augmenting hardened DSP processing units in an ASIC to provide additional flexibility for new filter algorithms or re-ordering of the DSP processing pipeline 
• Ability to provide RTL support for legacy JESD204B/C connectivity while being able to support changes to the recently released JESD204D specification and future versions 
• Enabling end-user-specific inline encryption, compression, and anomaly detection algorithms 

In summary, wherever there is a data converter, eFPGA provides flexibility and adaptability to optimize how ASICs manage and process incoming data, maximizing efficiency and extending product life to support new standards like JESD204E, which will be here before you know it.