Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for Mobile, Cloud, and IoT Platforms
April 8, 2015
Consumer demand for entertainment and communication is changing the architecture of your electronic devices. And Cadence is providing key IPs necessary for SoC developers to quickly bring their products to market. Today Cadence is unveiling its first-silicon results for both DDR4 and LPDDR4 IP on TSMC's 16nm FinFET Plus (16FF+) process, with test chips operating at 3200Mbps. This speed can support the computation requirements for tomorrow’s high-resolution video and data bandwidth requirements of mobile, cloud, and networking devices. Figure 1 shows the fully integrated LPDDR4 package-on-package (POP) test chip and memory.
To read the full article, click here
Related Semiconductor IP
- DDR4 Controller - Validates memory compliance, optimizes performance, ensures reliability
- Simulation VIP for DDR4 LRDIMM
- Simulation VIP for DDR4
- DDR4 IP solution
- DDR4 DFI Synthesizable Transactor
Related Blogs
- HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF
- Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC
- DDR4 & LPDDR4: The Race Is On!
- See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+
Latest Blogs
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security