Industry's First Verification IP for PCIe 7.0
In our recent blog, Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry's First PCIe 7.0 IP Solution, Synopsys announced the first comprehensive PCIe Express® Gen 7 (PCIe 7.0) IP Verification IP (VIP) solution to support the speed and low latency required for Artificial Intelligence (AI) applications in high performance computing designs.
PCI Express Evolution
Since its launch in 2003, PCI Express has undergone continuous advancements in technology, specification, and transfer speed, demonstrating its success as a standardization initiative and data transfer protocol. PCIe 5.0 powered cloud computing resources with 32G transfer speeds and CXL coherency, while PCIe 6.0 doubled performance to 64G transfer rates using Flow Control Units (FLITS) and PAM4 modulation for effective, low latency communication and coherency. PCIe 7.0's load-store capabilities and up to 512 GB/s of bandwidth for secure data transfers make it possible to connect multiple accelerators and process large, complex AI and machine learning models efficiently.
To read the full article, click here
Related Semiconductor IP
- MIPI SoundWire I3S Peripheral IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
Related Blogs
- How PCIe 7.0 is Boosting Bandwidth for AI Chips
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
- Industry's First Adopted VIP for PCIe 7.0
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained