Industry's First Verification IP for PCIe 7.0
In our recent blog, Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry's First PCIe 7.0 IP Solution, Synopsys announced the first comprehensive PCIe Express® Gen 7 (PCIe 7.0) IP Verification IP (VIP) solution to support the speed and low latency required for Artificial Intelligence (AI) applications in high performance computing designs.
PCI Express Evolution
Since its launch in 2003, PCI Express has undergone continuous advancements in technology, specification, and transfer speed, demonstrating its success as a standardization initiative and data transfer protocol. PCIe 5.0 powered cloud computing resources with 32G transfer speeds and CXL coherency, while PCIe 6.0 doubled performance to 64G transfer rates using Flow Control Units (FLITS) and PAM4 modulation for effective, low latency communication and coherency. PCIe 7.0's load-store capabilities and up to 512 GB/s of bandwidth for secure data transfers make it possible to connect multiple accelerators and process large, complex AI and machine learning models efficiently.
To read the full article, click here
Related Semiconductor IP
- Rabbit (TM) 5000 microprocessor
- Rabbit (TM) 4000 microprocessor
- M8051EW V3.0+ Fast 8-bit Microcontroller with on-chip debug
- M8051W V 5.0 Fast 8-bit Microcontroller
- M8052 8-bit Microcontroller
Related Blogs
- Building Verification Infrastructure for Complex PCIe Verification
- Industry's First Verification IP for Arm AMBA CHI-G
- How PCIe 7.0 is Boosting Bandwidth for AI Chips
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
Latest Blogs
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA
- Design IP Market Increased by All-time-high: 20% in 2024!