Industry's First Verification IP for PCIe 7.0
In our recent blog, Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry's First PCIe 7.0 IP Solution, Synopsys announced the first comprehensive PCIe Express® Gen 7 (PCIe 7.0) IP Verification IP (VIP) solution to support the speed and low latency required for Artificial Intelligence (AI) applications in high performance computing designs.
PCI Express Evolution
Since its launch in 2003, PCI Express has undergone continuous advancements in technology, specification, and transfer speed, demonstrating its success as a standardization initiative and data transfer protocol. PCIe 5.0 powered cloud computing resources with 32G transfer speeds and CXL coherency, while PCIe 6.0 doubled performance to 64G transfer rates using Flow Control Units (FLITS) and PAM4 modulation for effective, low latency communication and coherency. PCIe 7.0's load-store capabilities and up to 512 GB/s of bandwidth for secure data transfers make it possible to connect multiple accelerators and process large, complex AI and machine learning models efficiently.
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Related Semiconductor IP
- HBM4 PHY IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- VIP for Compute Express Link (CXL)
Related Blogs
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
- Industry's First Adopted VIP for PCIe 7.0
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)