Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
One of the hottest (or should I say coolest – because low power is so important) new standards is PCI Express® (PCIe) over M-PHY, or M-PCIe. To implement it properly, it’s essential that the controller and PHY work well together as the interface specification between them is, to put it mildly, loosely defined.
We just finished the PCI-SIG 2013 conference at the Santa Clara Convention Center, and our M-PCIe demo was a big hit. We actually demoed it for the first time the week of June 17, 2013, at the MIPI Alliance’s European Meeting in Warsaw.
It was fitting that Cadence would be the first to demonstrate the PHY and controller IP with high-speed links across M-PHYs. Cadence was one of the initial sponsors of this ECN. The Cadence design team actively participated in the discussions and contributed to the specification. Our design is a native RMMI based implementation, unlike implementations that convert PCIe to M-PCIe using a shim layer. The shortcut via the shim might be tempting, but does not help realize the power advantages of the protocol!
Related Semiconductor IP
- PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation
Related Blogs
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
- How to Verify Complex PIPE Interface Based PHY Designs?
- 4nm 112G-ELR SerDes PHY IP
- PHY IP: the last frontier of configurability?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?