DDR4 Controller IP, Cadence IP strategy... and Synopsys
April 18, 2011
I will share with you some strategic information released by Cadence last week about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.
To read the full article, click here
Related Semiconductor IP
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
Related Blogs
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems
Latest Blogs
- Silicon Insurance: Why eFPGA is Cheaper Than a Respin
- One Bit Error is Not Like Another: Understanding Failure Mechanisms in NVM
- Introducing CoreCollective for the next era of open collaboration for the Arm software ecosystem
- Integrating eFPGA for Hybrid Signal Processing Architectures
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity