Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)
This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related Blogs
- Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
- According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
- PCIe Gen4 Test Suite with Spec Linking Demo
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
Latest Blogs
- Trust at the Core: A Deep Dive into Hardware Root of Trust (HRoT)
- Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer
- LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5
- MIPI MPHY 6.0: Enabling Next-Generation UFS Performance
- How Does Crocodile Dundee Relate to AI Inference?