Bye-Bye DDRn Protocol?
In fact, this assertion is provocative, as the DDR4 protocol standard has just been released by JEDEC… after 10 years discussion around the protocol features. Yes, the first discussions about DDR4 have started ten years ago! Will DDR4 be used in the industry? The answer is certainly yes, and DDR4 will most probably be used for years. But memory controllers experts, like Graham Allan, Sr Marketing Manager at Synopsys (and active JEDEC member), consider that DDR4 will be the last protocol standard for interfacing SDRAM. We can expect the next protocol to finally escape from parallel bus based architecture, with clock, addresses and command signals being separated. The DDRn architecture is known to generate routing issues at PCB level, high power consumption and require a complex implementation at SoC level, leading chip maker to increasingly outsource DDRn memory controller. The latter is the positive point, as it allows the SoC designers to focus of the real differentiators. But why not going to high speed serial protocol, based on a 10 Gbps (or more) SerDes with embedded clock, like PCIe or Ethernet, to name a few?
To read the full article, click here
Related Semiconductor IP
- DDR PHY & DDR Controller IP
- DDR and LPDDR Combo PHY
- AMBA AHB Bus to DDR SDRAM Controller
- DDR SDRAM Controller
- DDR and DDR2 SDRAM Controller Intel® FPGA IP Core
Related Blogs
- Interface Protocols, USB3, PCI Express, MIPI, DDRn... the winner and losers in 2013
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- SystemVerilog Protocol Compliance: Why Source-code Test Suites?
- Overcoming the Protocol Debug Challenge
Latest Blogs
- Breaking the Silence: What Is SoundWire‑I3S and Why It Matters
- What It Will Take to Build a Resilient Automotive Compute Ecosystem
- The Blind Spot of Semiconductor IP Sales
- Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization
- UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC