SystemVerilog Protocol Compliance: Why Source-code Test Suites?
Here, Bernie DeLay explains the architecture and scope of the SystemVerilog source-code test suites included with the Synopsys VIP titles, and how they minimize the effort associated with protocol compliance testing. He uses a USB VIP in a DesignWare environment with AXI as an example.
Related Semiconductor IP
- Lightweight and Configurable Root-of-Trust Soft IP
- Message filter
- SSL/TLS Offload Engine
- TCP/UDP Offload Engine
- JPEG-LS Encoder IP
Related Blogs
- Synopsys CXL Protocol Verification Solutions Proven with Real World Vendor Devices at the CXL Compliance Test Event
- PCIe Gen4 - VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites
- VIP Architecture: Why Native SystemVerilog and UVM?
- PCIe: Monitors and Test Suites