DDR multi PHY
Overview
The DDR multiPHYs are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 SDRAM memories up to 1066 Mbps data rates and Mobile DDR (also referred to as mDDR and LPDDR) SDRAM memories up to 400 Mbps data rates. This particular PHY supports switching between DDR2 and DDR3 memories once a chip is in production. This “Lite” PHY does not go up to the full 1600 Mbps data rate targeted for DDR3. Instead, this is an area and feature optimized DDR2/DDR3 PHY for customers that want to go to market with DDR2 interfaces up to 1066 Mbps and also want an insurance policy against equivalent DDR3 devices becoming cheaper while their chip remains in the market. As part of the optimization of this PHY, a small number of the new features for DDR3, such as write leveling, are not supported as they are not supported by DDR2 SDRAMs.
Key Features
- ?Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
- ?Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
- ? Operating range of DC to 200MHz in Mobile DDR mode
- ? PHY Utility Block (PUBL) component
- ? DFI 2.1 compliant interface to controller
- ? At-speed loopback testing
- ? Configurable external data bus widths in 8-bit increments
- ? Permits operating with SDRAMs using data widths narrower than the implemented data width
- ? Programmable output and ODT impedance with dynamic PVT compensation
- ? Embedded Dynamic Drift Detection in the PHY to facilitate Dynamic Drift Compensation with the controller
- ? Utilizes Master and Slave DLLs for precise timing management
- ? Lane-based architecture (Byte Lane, Command Lane)
- ? Test modes supporting IDDq and DLL characterization
- ? Library-based hard-IP PHY to permit maximum flexibility while ensuring high data rates
- ? Full documentation including physical implementation guide
- ? Includes all required views for a typical ASIC design flow
Deliverables
- We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.
Technical Specifications
Foundry, Node
TSMC,40; SMIC,40,65; GF,40; UMC,40
Maturity
Silicon Proven
Availability
Immediate
GLOBALFOUNDRIES
Silicon Proven:
40nm
LP
SMIC
Silicon Proven:
40nm
LL
,
65nm
LL
TSMC
Silicon Proven:
40nm
LP
UMC
Silicon Proven:
40nm
LP
Related IPs
- DDR SDRAM Controller
- DDR SDRAM Controller
- DDR SDRAM Controller - Pipelined
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR SDRAM Controller supporting Altmemphy
- SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC