Avoiding Multi-Die System Re-spins with New Early Architecture Exploration Technology
Getting an early jump on architecture exploration of multi-die systems can yield valuable benefits, such as preventing costly design respins. However, the exploration process has traditionally been rather manual, with most designers relying on static spreadsheets and ad-hoc in-house tools. As a result, it’s challenging to meet key performance indicators (KPIs) or even project schedules.
Now, there’s a new dynamic, early system architecture exploration solution designed to accelerate architecture realization for multi-die systems: Synopsys Platform Architect for Multi-Die Systems.
The solution is built on the industry leading Synopsys Platform Architect™, which provides SystemC™ transaction-level modeling-based tools for early analysis and optimization of SoC architectures for performance and power. This new tool, validated by designers of AI and automotive multi-die systems, accounts for the complex interdependencies of multi-die systems. Read on to learn more about how this dynamic, model-based performance and power analysis and simulation technology can help mitigate the risks of system architecture decisions while enhancing turnaround times for multi-die system designs.
To read the full article, click here
Related Semiconductor IP
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
Related Blogs
- New Distributed Simulation Technology for Faster Simulation of Multi-Die Systems
- Imec and Synopsys Lower the Barriers to 2nm Technology With New Pathfinding Design Kit
- Cadence Transforms Chiplet Technology with First Arm-Based System Chiplet
- Rambus CryptoManager Root of Trust Solutions Tailor Security Capabilities to Specific Customer Needs with New Three-Tier Architecture