Virtual prototyping speeds mixed-signal IC design
(08/21/2006 9:00 AM EDT), EE Times
Current design trends for high performance systems-on-chip (SoCs) are prompting designers to adopt more and more analog/mixed signal (AMS) contents in the overall design. Unlike digital designs that are quantized in the time and amplitude domains, AMS designs are more complex because performance, noise and other factors need to be controlled continuously in time and amplitude domain with very strict tolerances.
While the cost and performance benefits of SoCs are well known, in reality the complexity of design and verification of AMS ICs are making cutting-edge designs very time consuming and error prone, hence cost ineffective. The problem is further exacerbated by the lack of skilled AMS designers and adequate EDA tools.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Analog & Mixed Signal IC Debug: A high precision ADC application
- Mixed-level modeling allows IC virtual prototypes
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- RTL Prototyping Brings Hardware Speeds to Functional Verification
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems