Virtual prototyping speeds mixed-signal IC design
Raja Mitra, Cadence Design Systems
(08/21/2006 9:00 AM EDT), EE Times
Current design trends for high performance systems-on-chip (SoCs) are prompting designers to adopt more and more analog/mixed signal (AMS) contents in the overall design. Unlike digital designs that are quantized in the time and amplitude domains, AMS designs are more complex because performance, noise and other factors need to be controlled continuously in time and amplitude domain with very strict tolerances.
While the cost and performance benefits of SoCs are well known, in reality the complexity of design and verification of AMS ICs are making cutting-edge designs very time consuming and error prone, hence cost ineffective. The problem is further exacerbated by the lack of skilled AMS designers and adequate EDA tools.
(08/21/2006 9:00 AM EDT), EE Times
Current design trends for high performance systems-on-chip (SoCs) are prompting designers to adopt more and more analog/mixed signal (AMS) contents in the overall design. Unlike digital designs that are quantized in the time and amplitude domains, AMS designs are more complex because performance, noise and other factors need to be controlled continuously in time and amplitude domain with very strict tolerances.
While the cost and performance benefits of SoCs are well known, in reality the complexity of design and verification of AMS ICs are making cutting-edge designs very time consuming and error prone, hence cost ineffective. The problem is further exacerbated by the lack of skilled AMS designers and adequate EDA tools.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- Analog & Mixed Signal IC Debug: A high precision ADC application
- Mixed-level modeling allows IC virtual prototypes
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- RTL Prototyping Brings Hardware Speeds to Functional Verification
Latest Articles
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation