The SoC design: What’s next for NoCs?
By Andy Nightingale, Arteris
EDN (January 24, 2025)
Today’s high-end system-on-chips (SoCs) rely heavily on sophisticated network-on-chip (NoC) technology to achieve performance and scalability. As the demands of artificial intelligence (AI), high-performance computing (HPC), and other compute-intensive applications continue to evolve, designing the next generation of SoCs will require even smarter and more efficient NoC solutions to meet these challenges.
Although these advancements present exciting opportunities, they also bring significant hurdles. SoC designers face rapid expansion in architecture, time-to-market pressures, scarcity of expertise, suboptimal utilization of resources, and disparate toolchains.
Exponential growth in SoC complexity
SoC designs have reached unprecedented levels of complexity, driven by advancements in process technologies and design tools. Now, SoCs typically include between 50 and 500+ IP blocks, ranging from processor cores and memory controllers to specialized accelerators for AI and graphics.
These blocks, which once contained just tens of thousands of transistors, now house anywhere from 1 million to over 1 billion transistors each.
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