Viewpoint: More to IP reuse than software tweaks
EE Times (02/25/2009 11:50 AM EST)
As long as the process technologists continue to make it practical to deploy an increasing number of gates, creative design engineers will find ambitious new ways to use those gates to build competitive advantage.
Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.
Leading edge semiconductor and consumer products companies will continue to differentiate their products beyond IP reuse with proprietary functionality implemented in hardware. In order to maintain their competitive edge, they increasingly turn to higher levels of abstraction and synthesis for creating these proprietary hardware blocks.
While it is certainly true that platform-based design and IP reuse reduces effort compared to creating new hardware in RTL, assembling existing IP blocks is not a complete strategy for creating new SoCs comprising tens of millions of gates. Ways to create custom hardware more efficiently than handwriting RTL are also needed.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Defining platform-based design
- Tools For Reprogrammability -> Platform-based design ups productivity
- Platform-Based Design: The Pragmatic Solution for SoCs
- Platform-Based Design Propels Growth in Europe
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems