Viewpoint: More to IP reuse than software tweaks
Mike Meredith, Forte Design Systems
EE Times (02/25/2009 11:50 AM EST)
As long as the process technologists continue to make it practical to deploy an increasing number of gates, creative design engineers will find ambitious new ways to use those gates to build competitive advantage.
Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.
Leading edge semiconductor and consumer products companies will continue to differentiate their products beyond IP reuse with proprietary functionality implemented in hardware. In order to maintain their competitive edge, they increasingly turn to higher levels of abstraction and synthesis for creating these proprietary hardware blocks.
While it is certainly true that platform-based design and IP reuse reduces effort compared to creating new hardware in RTL, assembling existing IP blocks is not a complete strategy for creating new SoCs comprising tens of millions of gates. Ways to create custom hardware more efficiently than handwriting RTL are also needed.
EE Times (02/25/2009 11:50 AM EST)
As long as the process technologists continue to make it practical to deploy an increasing number of gates, creative design engineers will find ambitious new ways to use those gates to build competitive advantage.
Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.
Leading edge semiconductor and consumer products companies will continue to differentiate their products beyond IP reuse with proprietary functionality implemented in hardware. In order to maintain their competitive edge, they increasingly turn to higher levels of abstraction and synthesis for creating these proprietary hardware blocks.
While it is certainly true that platform-based design and IP reuse reduces effort compared to creating new hardware in RTL, assembling existing IP blocks is not a complete strategy for creating new SoCs comprising tens of millions of gates. Ways to create custom hardware more efficiently than handwriting RTL are also needed.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- Defining platform-based design
- Tools For Reprogrammability -> Platform-based design ups productivity
- Platform-Based Design: The Pragmatic Solution for SoCs
- Platform-Based Design Propels Growth in Europe
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval