Viewpoint: Need to move beyond the network-on-chip
Ray Brinks, Vice President, Engineering, Sonics, Inc.
EE Times (01/04/2010 2:49 PM EST)
Over the last decade, designers have been content with standard connectivity methodologies to fulfill the needs of their system-on-chip (SoC) designs.
With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.
The inherent communications between on-chip cores is now taking on more of the comprehensive characteristics of a network rather than simply a bus. These characteristics include standard interface protocols, sockets at the edge of the network to allow cores to maintain a level of independence, and scalability so that the network can grow or shrink as needed. Enter the network-on-chip (NoC).
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- NoC Verification IP
- NoC System IP
- Non-Coherent Network-on-Chip (NOC)
- Coherent Network-on-Chip (NOC)
Related Articles
- Concepts and Implementation of the Philips Network-on-Chip
- A comparison of Network-on-Chip and Busses
- A Central Caching Network-on-chip Communication Architecture Design
- Synthesizable Switching Logic For Network-On-Chip Designs on 90nm Technologies
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval