Introduction to the Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module
Trevor martin gives a developer’s view of Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module.
Since its inception the ARM7 core has primarily been available as an IP core for incorporation into custom System on chip designs. With the launch of the LPC2106 the first member of the LPC2100 family Philips has introduced a standard chip featuring the 32-bit ARM7 processor on chip FLASH and SRAM with a range of general purpose peripherals in low pin count packages. However this on it own does not necessarily make a successful microcontroller, as always the devil is in the detail and this article will look at some of the key features of the LPC2100 family that help to successfully integrate the ARM7 CPU into a standard microcontroller architecture.
Click here to read more ....
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- FPGAs - The Logical Solution to the Microcontroller Shortage
- How to Elevate RRAM and MRAM Design Experience to the Next Level
- NoCs and the transition to multi-die systems using chiplets
- The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor