How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)
September 20, 2006 -- pldesignline.com
Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").
This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various "sleep modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many advantages over sleep modes, including the ability to use selected portions of the device. These CPLDs are built on an inherently ultra-low-power patented technology that reduces standby current to as low as 20 microamps.
The technology, known as Fast Zero Power, enables you to build fast, low power handheld consumer devices using programmable logic. Internal input/output (I/O) gating is an advanced feature of these devices that enables the design to gate out unwanted signals during actual operation, thus saving additional power from unwanted toggling of I/Os and downstream logic. You have to ability to select the inputs and outputs for gating, and turn them on and off at will.
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related White Papers
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design