How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)
By Roger Seaman, Xilinx
September 20, 2006 -- pldesignline.com
Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").
This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various "sleep modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many advantages over sleep modes, including the ability to use selected portions of the device. These CPLDs are built on an inherently ultra-low-power patented technology that reduces standby current to as low as 20 microamps.
The technology, known as Fast Zero Power, enables you to build fast, low power handheld consumer devices using programmable logic. Internal input/output (I/O) gating is an advanced feature of these devices that enables the design to gate out unwanted signals during actual operation, thus saving additional power from unwanted toggling of I/Os and downstream logic. You have to ability to select the inputs and outputs for gating, and turn them on and off at will.
September 20, 2006 -- pldesignline.com
Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").
This article discusses the differences between low power CPLDs with a built-in I/O gating feature, and the various "sleep modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many advantages over sleep modes, including the ability to use selected portions of the device. These CPLDs are built on an inherently ultra-low-power patented technology that reduces standby current to as low as 20 microamps.
The technology, known as Fast Zero Power, enables you to build fast, low power handheld consumer devices using programmable logic. Internal input/output (I/O) gating is an advanced feature of these devices that enables the design to gate out unwanted signals during actual operation, thus saving additional power from unwanted toggling of I/Os and downstream logic. You have to ability to select the inputs and outputs for gating, and turn them on and off at will.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
- How to build a better DC/DC regulator using FPGAs
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS