Transfer from FPGAs for prototype to ASICs for production
Terry Danzer and Cale Entzel, ON Semiconductor
EETimes (11/28/2011 1:38 PM EST)
Field-programmable gate arrays (FPGAs) are a valuable technology for designing and prototyping digital logic into today’s applications. However, high FPGA unit cost can sometimes prohibit higher volume production. Several alternatives exist for transferring a digital design, implemented with an FPGA, into higher-volume production. Low-cost solutions such as structured application-specific integrated circuits (ASICs), cell-based ICs, and gate arrays offer higher performance, lower power consumption, higher levels of integration, and better response to radiation effects. The idea of migrating an FPGA design into an ASIC can be overwhelming to a design team, but careful planning and partnering with an experienced ASIC vendor can significantly ease the process.
Designing a new product in an FPGA allows for design modifications to be made quickly in hardware. Once the design code is stable and the product is ready for production, a migration from an FPGA to an ASIC can cut the production unit cost by up to 50%. The low non-recurring engineering (NRE) charges associated with a mid-range ASIC solution coupled with a much lower unit price point make this strategy a powerful tool in achieving low overall expense, giving users a competitive cost advantage in the market.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- Improving ASIC Design Verification using FPGAs and Structured ASICs
- Using customizable MCUs to bridge the gap between dedicated SoC ASSPs, ASICs and FPGAs: Part 1
- SATA Connectivity solutions for Xilinx FPGAs
- How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events