Using FPGAs to improve your wireless subsystem's performance
Embedded.com (08/25/08, 09:05:00 AM EDT)
You can realize significant improvements in the performance of signal processing functions in wireless systems. How? By taking advantage of the flexibility of FPGA fabric and the embedded DSP blocks in current FPGA architectures for operations that can benefit from parallelism.
Common examples of operations found in wireless applications include FIR filtering, Fast Fourier Transforms (FFTs), digital down and up conversion and Forwared Error Correction (FEC) blocks.
By offloading operations that require high-speed parallel processing onto the FPGA and leaving operations that require high-speed serial processing on the processor, overall system performance and cost can be optimized while lowering system requirements.
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
Related White Papers
- Subsystem design key to wireless gaming
- MPEG Standards -> End user reaps benefit of wireless multimedia structure
- Wireless lan standard holds back Bluetooth
- Reuse eases wireless SoC efforts
Latest White Papers
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems
- CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs