Using FPGAs to improve your wireless subsystem's performance
By Dave Nicklin and Tom Hill from Xilinx, Inc.
Embedded.com (08/25/08, 09:05:00 AM EDT)
You can realize significant improvements in the performance of signal processing functions in wireless systems. How? By taking advantage of the flexibility of FPGA fabric and the embedded DSP blocks in current FPGA architectures for operations that can benefit from parallelism.
Common examples of operations found in wireless applications include FIR filtering, Fast Fourier Transforms (FFTs), digital down and up conversion and Forwared Error Correction (FEC) blocks.
By offloading operations that require high-speed parallel processing onto the FPGA and leaving operations that require high-speed serial processing on the processor, overall system performance and cost can be optimized while lowering system requirements.
Embedded.com (08/25/08, 09:05:00 AM EDT)
You can realize significant improvements in the performance of signal processing functions in wireless systems. How? By taking advantage of the flexibility of FPGA fabric and the embedded DSP blocks in current FPGA architectures for operations that can benefit from parallelism.
Common examples of operations found in wireless applications include FIR filtering, Fast Fourier Transforms (FFTs), digital down and up conversion and Forwared Error Correction (FEC) blocks.
By offloading operations that require high-speed parallel processing onto the FPGA and leaving operations that require high-speed serial processing on the processor, overall system performance and cost can be optimized while lowering system requirements.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- Subsystem design key to wireless gaming
- MPEG Standards -> End user reaps benefit of wireless multimedia structure
- Wireless lan standard holds back Bluetooth
- Reuse eases wireless SoC efforts
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks