Using FPGAs to improve your wireless subsystem's performance
Embedded.com (08/25/08, 09:05:00 AM EDT)
You can realize significant improvements in the performance of signal processing functions in wireless systems. How? By taking advantage of the flexibility of FPGA fabric and the embedded DSP blocks in current FPGA architectures for operations that can benefit from parallelism.
Common examples of operations found in wireless applications include FIR filtering, Fast Fourier Transforms (FFTs), digital down and up conversion and Forwared Error Correction (FEC) blocks.
By offloading operations that require high-speed parallel processing onto the FPGA and leaving operations that require high-speed serial processing on the processor, overall system performance and cost can be optimized while lowering system requirements.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- Subsystem design key to wireless gaming
- MPEG Standards -> End user reaps benefit of wireless multimedia structure
- Wireless lan standard holds back Bluetooth
- Reuse eases wireless SoC efforts
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design