Using FPGAs to improve your wireless subsystem's performance
By Dave Nicklin and Tom Hill from Xilinx, Inc.
Embedded.com (08/25/08, 09:05:00 AM EDT)
You can realize significant improvements in the performance of signal processing functions in wireless systems. How? By taking advantage of the flexibility of FPGA fabric and the embedded DSP blocks in current FPGA architectures for operations that can benefit from parallelism.
Common examples of operations found in wireless applications include FIR filtering, Fast Fourier Transforms (FFTs), digital down and up conversion and Forwared Error Correction (FEC) blocks.
By offloading operations that require high-speed parallel processing onto the FPGA and leaving operations that require high-speed serial processing on the processor, overall system performance and cost can be optimized while lowering system requirements.
Embedded.com (08/25/08, 09:05:00 AM EDT)
You can realize significant improvements in the performance of signal processing functions in wireless systems. How? By taking advantage of the flexibility of FPGA fabric and the embedded DSP blocks in current FPGA architectures for operations that can benefit from parallelism.
Common examples of operations found in wireless applications include FIR filtering, Fast Fourier Transforms (FFTs), digital down and up conversion and Forwared Error Correction (FEC) blocks.
By offloading operations that require high-speed parallel processing onto the FPGA and leaving operations that require high-speed serial processing on the processor, overall system performance and cost can be optimized while lowering system requirements.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- Subsystem design key to wireless gaming
- MPEG Standards -> End user reaps benefit of wireless multimedia structure
- Wireless lan standard holds back Bluetooth
- Reuse eases wireless SoC efforts
Latest Articles
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation