Using FPGAs in Mobile Heterogeneous Computing Architectures
Abdullah Raouf, Lattice Semiconductor
EETimes (1/13/2017 05:40 PM EST)
Since "context-aware" systems must be "always on" to track changes in the environment, these capabilities represent a potentially significant drain on system power.
Today's mobile systems are more intelligent than ever. As users demand more functionality, designers are continually adding to a growing list of embedded sensors. Image sensors support functions such as gesture and facial recognition, eye tracking, proximity, depth, and movement perception. Health sensors monitor the user's EKG, EEG, EMG, and temperature. Audio sensors add voice recognition, phrase detection, and location-sensing services.
Many of these same devices now offer "context-aware" subsystems that allow the system to initiate highly advanced, task-enhancing decisions without prompting the user. For example, temperature, chemical, infrared, and pressure sensors can evaluate safety risks and track a user's health in dangerous environments. Precision image sensors and ambient light sensors can boost image resolution and display readability automatically as environmental conditions change.
To read the full article, click here
Related Semiconductor IP
- Single instance HW Lattice PQC ultra accelerator
- Highly configurable HW Lattice PQC ultra acceleration in AXI4 & PCIe systems
- CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
- Lattice Mico8 Open, Free Soft Microcontroller
- LatticeMico32 Open, Free 32-Bit Soft Processor
Related White Papers
- ARM Mali-T604 tips mobile graphics, computing, and IP trends
- The case for integrating FPGA fabrics with CPU architectures
- Sharing NVMe SSDs for heterogeneous architectures
- The rise of FPGA technology in High-Performance Computing
Latest White Papers
- cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications
- From Principles to Practice: A Systematic Study of LLM Serving on Multi-core NPUs
- Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
- A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
- Runtime Energy Monitoring for RISC-V Soft-Cores