CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
By Simone Manoni 1, Emanuele Parisi 2, Riccardo Tedeschi 1, Davide Rossi 1,3, Andrea Acquaviva 1, Andrea Bartolini 1
1 Department of Electrical, Electronic, and Information Engineering - University of Bologna, Italy
2 High Performance Domain-Specific Architectures Group - Barcelona Supercomputing Center, Spain
3 Department of Digital Design and Open Hardware - Chips-IT, Italy

Abstract
This work presents the first design, integration, and evaluation of the standard RISC-V extensions for Control-Flow Integrity (CFI). The Zicfiss and Zicfilp extensions aim at protecting the execution of a vulnerable program from control-flow hijacking attacks through the implementation of security mechanisms based on shadow stack and landing pad primitives. We introduce two independent and configurable hardware units implementing forward-edge and backward-edge control-flow protection, fully integrated into the open-source CVA6 core. Our design incurs in only 1.0% area overhead when synthesized in 22 nm FDX technology, and up to 15.6% performance overhead based on evaluation with the MiBench automotive benchmark subset. We release the complete implementation as open source.
Index Terms — Control-Flow Integrity, Shadow Stack, Landing Pad, RISC-V
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related Articles
- A closer look at security verification for RISC-V processors
- What is JESD204C? A quick glance at the standard
- OpenAccess: first impressions at AMD
- Inside the Xilinx Kintex-7 FPGA: A closer look at the first FPGA to use HKMG technology
Latest Articles
- System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
- CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design