AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance

By Seungkwan Kang ¹, Seungjun Lee ¹, Donghyun Gouk ², Miryeong Kwon ², Hyunkyu Choi ², Junhyeok Jang ², Sangwon Lee ², Huiwon Choi ¹, Jie Zhang ³, Wonil Choi ⁴, Mahmut Taylan Kandemir ⁵, Myoungsoo Jung ^1,2
1 Computer Architecture and Memory Systems Laboratory, KAIST, 
² Panmnesia, Inc.,
³ Peking University, 
⁴ Hanyang University, 
⁵ Pennsylvania State University

Abstract

Graph neural network (GNN) inference faces significant bottlenecks in preprocessing, which often dominate overall inference latency. We introduce AutoGNN, an FPGA-based accelerator designed to address these challenges by leveraging FPGA’s reconfigurability and specialized components. AutoGNN adapts to diverse graph inputs, efficiently performing computationally intensive tasks such as graph conversion and sampling. By utilizing components like adder trees, AutoGNN executes reduction operations in constant time, overcoming the limitations of serialization and synchronization on GPUs.

AutoGNN integrates unified processing elements (UPEs) and single-cycle reducers (SCRs) to streamline GNN preprocessing. UPEs enable scalable parallel processing for edge sorting and unique vertex selection, while SCRs efficiently handle sequential tasks such as pointer array construction and subgraph reindexing. A user-level software framework dynamically profiles graph inputs, determines optimal configurations, and reprograms AutoGNN to handle varying workloads. Implemented on a 7nm enterprise FPGA, AutoGNN achieves up to 9.0× and 2.1× speedup compared to conventional and GPU-accelerated preprocessing systems, respectively, enabling high-performance GNN preprocessing across diverse datasets.

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